Use predefined bit manipulation macros

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Rihards Skuja 2018-01-02 14:18:30 +02:00
parent b7458e4bd3
commit e6ec28b04c
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2 changed files with 36 additions and 39 deletions

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@ -18,14 +18,11 @@ References:
#include <avr/io.h>
//setup connection
#define DS18B20_PORT PORTC
#define DS18B20_DDR DDRC
#define DS18B20_PIN PINC
#define DS18B20_DQ PC0
#define DS18B20_BIT PC0
//commands
#define DS18B20_CMD_CONVERTTEMP 0x44
#define DS18B20_CMD_RSCRATCHPAD 0xbe
#define DS18B20_CMD_WSCRATCHPAD 0x4e
@ -41,7 +38,7 @@ References:
//stop any interrupt on read
#define DS18B20_STOPINTERRUPTONREAD 1
//functions
uint8_t ds18b20_reset(void);
void ds18b20_writebit(uint8_t bit);
uint8_t ds18b20_readbit(void);

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@ -10,8 +10,8 @@ Please refer to LICENSE file for licensing information.
#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#include "ds18b20.h"
#include "common.h"
#include "temperature.h"
/*
* ds18b20 init
@ -21,16 +21,16 @@ uint8_t ds18b20_reset()
uint8_t i;
// low for 480us
DS18B20_PORT &= ~(1 << DS18B20_DQ); //low
DS18B20_DDR |= (1 << DS18B20_DQ); //output
CLR(DS18B20_PORT, DS18B20_BIT);
SET(DS18B20_DDR, DS18B20_BIT);
_delay_us(480);
// release line and wait for 60uS
DS18B20_DDR &= ~(1 << DS18B20_DQ); //input
CLR(DS18B20_DDR, DS18B20_BIT);
_delay_us(60);
// get value and wait 420us
i = (DS18B20_PIN & (1 << DS18B20_DQ));
i = CHK(DS18B20_PIN, DS18B20_BIT);
_delay_us(420);
// return the read value, 0=ok, 1=error
@ -43,17 +43,17 @@ uint8_t ds18b20_reset()
void ds18b20_writebit(uint8_t bit)
{
// low for 1uS
DS18B20_PORT &= ~(1 << DS18B20_DQ); //low
DS18B20_DDR |= (1 << DS18B20_DQ); //output
CLR(DS18B20_PORT, DS18B20_BIT);
SET(DS18B20_DDR, DS18B20_BIT);
_delay_us(1);
// if we want to write 1, release the line (if not will keep low)
if (bit)
DS18B20_DDR &= ~(1 << DS18B20_DQ); //input
CLR(DS18B20_DDR, DS18B20_BIT);
// wait 60uS and release the line
_delay_us(60);
DS18B20_DDR &= ~(1 << DS18B20_DQ); //input
DS18B20_DDR &= ~(1 << DS18B20_BIT);
}
/*
@ -64,16 +64,16 @@ uint8_t ds18b20_readbit(void)
uint8_t bit = 0;
// low for 1uS
DS18B20_PORT &= ~(1 << DS18B20_DQ); //low
DS18B20_DDR |= (1 << DS18B20_DQ); //output
CLR(DS18B20_PORT, DS18B20_BIT);
SET(DS18B20_DDR, DS18B20_BIT);
_delay_us(1);
// release line and wait for 14uS
DS18B20_DDR &= ~(1 << DS18B20_DQ); //input
CLR(DS18B20_DDR, DS18B20_BIT);
_delay_us(14);
// read the value
if (DS18B20_PIN & (1 << DS18B20_DQ))
if (CHK(DS18B20_PIN, DS18B20_BIT))
bit = 1;
// wait 45uS and return read value